View SST39LF200A-45-4C-EK_8164572.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

?2007 silicon storage technology, inc. s71117-09-000 2/07 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. data sheet features: ? organized as 128k x16 / 256k x16 / 512k x16 ? single voltage read and write operations ? 3.0-3.6v for sst39lf200a/400a/800a ? 2.7-3.6v for sst39vf200a/400a/800a ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 14 mhz) ? active current: 9 ma (typical) ? standby current: 3 a (typical) ? sector-erase capability ? uniform 2 kword sectors ? block-erase capability ? uniform 32 kword blocks ? fast read access time ? 45 and 55 ns for sst39lf200a ? 55 ns for sst39lf400a/800a ? 70 ns for sst39vf200a/400a/800a ? latched address and data ? fast erase and word-program ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? word-program time: 14 s (typical) ? chip rewrite time: 2 seconds (typical) for sst39lf/vf200a 4 seconds (typical) for sst39lf/vf400a 8 seconds (typical) for sst39lf/vf800a ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 48-lead tsop (12mm x 20mm) ? 48-ball tfbga (6mm x 8mm) ? 48-ball wfbga (4mm x 6mm) ? 48-bump xflga (4mm x 6mm) for 4m and 8m ? all non-pb (lead-free) devices are rohs compliant product description the sst39lf200a/400a/800a and sst39vf200a/400a/ 800a devices are 128k x16 / 256k x16 / 512k x16 cmos multi-purpose flash (mpf) manufactured with sst propri- etary, high-performance cmos superflash technology. the split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst39lf200a/400a/800a write (program or erase) with a 3.0-3.6v power supply. the sst39vf200a/400a/800a write (program or erase) with a 2.7-3.6v power supply. these devices conform to jedec standard pinouts for x16 memories. featuring high-performance word-program, the sst39lf200a/400a/800a and sst39vf200a/400a/ 800a devices provide a typical word-program time of 14 sec. the devices use toggle bit or data# polling to detect the completion of the program or erase operation. to pro- tect against inadvertent write, they have on-chip hardware and software data protection schemes. designed, manu- factured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endur- ance of 100,000 cycles. data retention is rated at greater than 100 years. the sst39lf200a/400a/800a and sst39vf200a/400a/ 800a devices are suited for applications that require con- venient and economical updating of program, configura- tion, or data memory. for all system applications, they significantly improve performanc e and reliability, while low- ering power consumption. they inherently use less energy during erase and program than alternative flash technolo- gies. when programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed dur- ing any erase or program operation is less than alternative flash technologies. these devices also improve flexibility while lowering the cost for program, data, and configura- tion storage applications. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/program cycles. 2 mbit / 4 mbit / 8 mbit (x16) multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39v f400a / sst39vf800a sst39lf/vf200a / 400a / 800a3.0 & 2.7v 2mb / 4mb / 8mb (x16) mpf memories
2 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 to meet surface mount requirements, the sst39lf200a/ 400a/800a and sst39vf200a/400a/800a are offered in 48-lead tsop packages and 48-ball tfbga packages as well as micro-packages. see figures 2, 3, and 4 for pin assignments. device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latc hed on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the sst39lf200a/400a/800a and sst39vf200a/400a/800a is cont rolled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is con- sumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 5). word-program operation the sst39lf200a/400a/800a and sst39vf200a/400a/ 800a are programmed on a word-by-word basis. before programming, the sector where the word exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initiated, will be completed within 20 s. see figures 6 and 7 for we# and ce# controlled program operation timing diagrams and figure 18 for flowcharts. during the program operation, the only valid reads are data# polling and tog- gle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. sector/block-e rase operation the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. the sst39lf200a/400a/800a and sst39vf200a/400a/800a offers both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uniform block size of 32 kword. the sector- erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of- erase operation can be determined using either data# polling or toggle bit methods. see figures 11 and 12 for timing waveforms. any commands issued during the sec- tor- or block-erase operation are ignored. chip-erase operation the sst39lf200a/400a/800a and sst39vf200a/400a/ 800a provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire de vice must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 10 for timing diagram, and figure 21 for the flowchart. any commands issued dur- ing the chip-erase operation are ignored. write operation status detection the sst39lf200a/400a/800a and sst39vf200a/400a/ 800a provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation.
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 3 ?2007 silicon storage technology, inc. s71117-09-000 2/07 the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. data# polling (dq 7 ) when the sst39lf200a/400a/800a and sst39vf200a/ 400a/800a are in the internal program operation, any attempt to read dq 7 will produce the co mplement of the true data. once the program operation is completed, dq 7 will produce true data. no te that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s . during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 8 fo r data# polling timing diagram and figure 19 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 9 for toggle bit timing diagram and figure 19 for a flowchart. data protection the sst39lf200a/400a/800a and sst39vf200a/400a/ 800a provide both hardware and software features to pro- tect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection : a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection : the write operation is inhibited when v dd is less than 1.5v. write inhibit mode : forcing oe# low, ce# high, or we# high will inhibit the write oper ation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst39lf200a/400a/800a and sst39vf200a/400a/ 800a provide the jedec approved software data protec- tion scheme for all data alteration operations, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six- byte sequence. this group of devices are shipped with the software data protection per- manently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode within trc. the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) the sst39lf200a/400a/800a and sst39vf200a/400a/ 800a also contain the cfi info rmation to describe the char- acteristics of the device. in order to enter the cfi query mode, the system must write three-byte sequence, same as software id entry command with 98h (cfi query com- mand) to address 5555h in the last byte sequence. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 5 through 9. the system must write the cfi exit command to return to read mode from the cfi query mode.
4 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 product identification the product identification mode identifies the devices as the sst39lf/vf200a, sst39lf/vf400a and sst39lf/ vf800a and manufacturer as sst. this mode may be accessed by software operations. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 4 for software operation, figure 13 for the software id entry and read timing diagram, and figure 20 for the software id entry command sequence flowchart. product identification mode exit/ cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/ cfi exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 15 for timing waveform, and figure 20 for a flowchart. figure 1: functional block diagram table 1: product identification address data manufacturer?s id 0000h 00bfh device id sst39lf/vf200a 0001h 2789h sst39lf/vf400a 0001h 2780h sst39lf/vf800a 0001h 2781h t1.3 1117 y-decoder i/o buffers and data latches 1117 b1.2 address buffer & latches x-decoder dq 15 - dq 0 memory address oe# ce# we# superflash memory control logic
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 5 ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 2: pin assignments for 48-lead tsop figure 3: pin assignments for 48-ball tfbga a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# nc nc nc nc nc nc a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1117 48-tsop p01.2 standard pinout top view die up sst39lf/vf200a a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# nc nc nc nc nc a17 a7 a6 a5 a4 a3 a2 a1 sst39lf/vf400a a15 a14 a13 a12 a11 a10 a9 a8 nc nc we# nc nc nc nc a18 a17 a7 a6 a5 a4 a3 a2 a1 sst39lf/vf800a sst39lf/vf200a a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 sst39lf/vf400a a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 sst39lf/vf800a a13 a9 we# nc a7 a3 a12 a8 nc nc nc a4 a14 a10 nc nc a6 a2 a15 a11 nc nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 1117 48-tfbga p02_2.0 sst39lf/vf200a top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h a13 a9 we# nc a7 a3 a12 a8 nc nc a17 a4 a14 a10 nc nc a6 a2 a15 a11 nc nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 1117 48-tfbga p02_4.0 sst39lf/vf400a top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h a13 a9 we# nc a7 a3 a12 a8 nc nc a17 a4 a14 a10 nc a18 a6 a2 a15 a11 nc nc a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 1117 48-tfb g a p02_8.0 sst39lf/vf800a top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h
6 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 4: pin assignments for 48 -ball wfbga and 48-bump xflga a2 a1 a0 ce# v ss a4 a3 a5 dq8 oe# dq0 a6 a7 nc dq10 dq9 dq1 a17 nc nc dq2 nc dq3 nc v dd we# dq12 nc nc nc dq13 a9 a10 a8 dq4 dq5 dq14 a11 a13 a12 dq11 dq6 dq15 a14 a15 a16 dq7 v ss top view (balls facing down) a b c d e f g h j k l 6 5 4 3 2 1 1117 48-xflga p03_4.0 sst39lf/vf400a a2 a1 a0 ce# v ss a4 a3 a5 dq8 oe# dq0 a6 a7 a18 dq10 dq9 dq1 a17 nc nc dq2 nc dq3 nc v dd we# dq12 nc nc nc dq13 a9 a10 a8 dq4 dq5 dq14 a11 a13 a12 dq11 dq6 dq15 a14 a15 a16 dq7 v ss top view (balls facing down) a b c d e f g h j k l 6 5 4 3 2 1 1117 48-xflga p03_8.0 sst39lf/vf800a a2 a1 a0 ce# v ss a4 a3 a5 dq8 oe# dq0 a6 a7 nc dq10 dq9 dq1 nc nc nc dq2 nc dq3 nc v dd we# dq12 nc nc nc dq13 a9 a10 a8 dq4 dq5 dq14 a11 a13 a12 dq11 dq6 dq15 a14 a15 a16 dq7 v ss top view (balls facing down) a b c d e f g h j k l 6 5 4 3 2 1 1117 48-xflga p03_2.0 sst39vf200a
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 7 ?2007 silicon storage technology, inc. s71117-09-000 2/07 table 2: pin description symbol pin name functions a ms 1 -a 0 address inputs to provide memory addresses. during sector-erase a ms -a 11 address lines will select the sector. during block-erase a ms -a 15 address lines will select the block. dq 15 -dq 0 data input/output to ou tput data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply vo ltage: 3.0-3.6v for sst39lf200a/400a/800a 2.7-3.6v for sst39vf200a/400a/800a v ss ground nc no connection unconnected pins. t2.2 1117 1. a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a, and a 18 for sst39lf/vf800a table 3: operation modes selection mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.4 1117
8 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 table 4: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55 h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 555 5h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5,6 5555h aah 2aaah 55h 5555h 90h cfi query entry 5 5555h aah 2aaah 55h 5555h 98h software id exit 7 / cfi exit xxh f0h software id exit 7 / cfi exit 5555h aah 2aaah 55h 5555h f0h t4.3 1117 1. address format a 14 -a 0 (hex), addresses a ms- a 15 can be v il or v ih , but no other value, for the command sequence. a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a, and a 18 for sst39lf/vf800a 2. dq 15 -dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word address 4. sa x for sector-erase; uses a ms -a 11 address lines ba x for block-erase; uses a ms -a 15 address lines 5. the device does not remain in software product id mode if powered down. 6. with a ms -a 1 = 0; sst manufacturer?s id = 00bfh, is read with a 0 = 0, sst39lf/vf200a device id = 2789h, is read with a 0 = 1. sst39lf/vf400a device id = 2780h, is read with a 0 = 1. sst39lf/vf800a device id = 2781h, is read with a 0 = 1. 7. both software id exit operations are equivalent table 5: cfi query identification string 1 for sst39lf200a/400a/800a and sst39vf200a/400a/800a 1. refer to cfi publication 100 for more details. address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0001h primary oem command set 14h 0007h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t5.0 1117
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 9 ?2007 silicon storage technology, inc. s71117-09-000 2/07 table 6: system interface information for sst39lf200a/400a/800a and sst39vf200a/400a/800a address data data 1bh 0027h 1 v dd min (program/erase) 0030h 1 dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min (00h = no v pp pin) 1eh 0000h v pp max (00h = no v pp pin) 1fh 0004h typical time out for word-program 2 n s (2 4 = 16 s) 20h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 0006h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 4 = 32 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 6 = 128 ms) t6.2 1117 1. 0030h for sst39lf200a/400a/800a and 0027h for sst39vf200a/400a/800a table 7: device geometry information for sst39lf/vf200a address data data 27h 0012h device size = 2 n byte (12h = 18; 2 18 = 256 kbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 2ch 0002h number of erase sector/block sizes supported by device 2dh 003fh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 2eh 0000h y = 63 + 1 = 64 sectors (003fh = 63) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 0003h block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 3 + 1 = 4 blocks (0003h = 3) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t7.2 1117
10 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 table 8: device geometry information for sst39lf/vf400a address data data 27h 0013h device size = 2 n byte (13h = 19; 2 19 = 512 kbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 007fh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 2eh 0000h y = 127 + 1 = 128 sectors (007fh = 127) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 0007h block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 7 + 1 = 8 blocks (0007h = 7) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t8.1 1117 table 9: device geometry information for sst39lf/vf800a address data data 27h 0014h device size = 2 n bytes (14h = 20; 2 20 = 1 mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = numb er of sectors; z x 256b = sector size) 2eh 0000h y = 255 + 1 = 256 sectors (00ffh = 255) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 000fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 15 + 1 = 16 blocks (000fh = 15) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t9.0 1117
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 11 ?2007 silicon storage technology, inc. s71117-09-000 2/07 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. excluding certain with-pb 32-plcc units, all packages are 260 c capable in both non-pb and with-pb solder versions. certain with-pb 32-plcc package types are capable of 240 c for 10 seconds; please consult the factory for the latest information. 2. outputs shorted for no more than one second. no more than one output shorted at a time. operating range: sst39lf200a/400a/800a range ambient temp v dd commercial 0c to +70c 3.0-3.6v operating range: sst39vf200a/400a/800a range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf for sst39lf200a/400a/800a output load . . . . . . . . . . . . . . . . . . . . c l = 100 pf for sst39vf200a/400a/800a see figures 16 and 17
12 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 table 10: dc operating characteristics v dd = 3.0-3.6v for sst39lf200a/400a/800a and 2.7-3.6v for sst39vf200a/400a/800a 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht, at f=1/t rc min, v dd =v dd max read 2 30 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 30 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 20 a ce#=v ihc , v dd =v dd max i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v dd =v dd min v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t10.7 1117 1. typical conditions for the active current shown on the front data sheet page are average values at 25c (room temperature), and v dd = 3v for vf devices. not 100% tested. 2. values are for 70 ns conditions. see the multi-purpose flash power rating application note for further information. table 11: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t11.0 1117 table 12: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t12.0 1117 table 13: reliability characteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cycl e minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t13.2 1117
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 13 ?2007 silicon storage technology, inc. s71117-09-000 2/07 ac characteristics table 14: read cycle timing parameters v dd = 3.0-3.6v symbol parameter sst39lf200a-45 sst39lf200a/400a/800a-55 units minmaxminmax t rc read cycle time 45 55 ns t ce chip enable access time 45 55 ns t aa address access time 45 55 ns t oe output enable access time 30 30 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 15 15 ns t ohz 1 oe# high to high-z output 15 15 ns t oh 1 output hold from address change 0 0 ns t14.7 1117 table 15: read cycle timing parameters v dd = 2.7-3.6v symbol parameter sst39vf200a/400a/800a-70 units min max t rc read cycle time 70 ns t ce chip enable access time 70 ns t aa address access time 70 ns t oe output enable access time 35 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 ns t olz 1 oe# low to active output 0 ns t chz 1 ce# high to high-z output 20 ns t ohz 1 oe# high to high-z output 20 ns t oh 1 output hold from address change 0 ns t15.7 1117
14 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 table 16: program/erase cycle timing parameters symbol parameter min max units t bp word-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 100 ms t16.0 1117 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er.
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 15 ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 5: read cycle timing diagram figure 6: we# controlled program cycle timing diagram 1117 f03.2 address a ms-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a and a 18 for sst39lf/vf800a 1117 f04.4 address a ms-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a and a 18 for sst39lf/vf800a x can be v il or v ih , but no other value.
16 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 7: ce# controlled prog ram cycle timing diagram figure 8: data# polling timing diagram 1117 f05.4 address a ms-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a and a 18 for sst39lf/vf800a x can be v il or v ih, but no other value. 1117 f06.3 address a ms-0 dq 7 data data# data# data we# oe# ce# t oeh t oe t ce t oes note: a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a and a 18 for sst39lf/vf800a
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 17 ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 9: toggle bit timing diagram figure 10: we# controlled chip-erase timing diagram 1117 f07.3 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a and a 18 for sst39lf/vf800a 1117 f08.7 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 16) a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a and a 18 for sst39lf/vf800a x can be v il or v ih , but no other value.
18 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 11: we# controlled block-erase timing diagram figure 12: we# controlled sector-erase timing diagram 1117 f17.9 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# controlled block-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 16) ba x = block address a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a and a 18 for sst39lf/vf800a x can be v il or v ih , but no other value. 1117 f18.8 address a ms-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 16) sa x = sector address a ms = most significant address a ms = a 16 for sst39lf/vf200a, a 17 for sst39lf/vf400a and a 18 for sst39lf/vf800a x can be v il or v ih , but no other value.
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 19 ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 13: software id entry and read figure 14: cfi query entry and read 1117 f09.4 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 device id = 2789h for sst39lf/vf200a, 2780h for sst39lf/vf400a and 2781h for sst39lf/vf800a note: x can be v il or v ih , but no other value. 1117 f20.1 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih , but no other value.
20 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 15: software id exit/cfi exit 1117 f10.1 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value.
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 21 ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 16: ac input/output reference waveforms figure 17: a test load example 1117 f11.1 reference points output input? v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1117 f12.1 to tester to dut c l
22 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 18: word-program algorithm 1117 f13.4 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but no other value.
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 23 ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 19: wait options 1117 f14.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
24 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 20: software id/cfi command flowcharts 1117 f15.4 load data: xxaah address: 5555h software id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h cfi query entry command sequence load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h software id exit/cfi exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation note: x can be v il or v ih , but no other value.
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 25 ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 21: erase command sequence 1117 f16.5 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh note: x can be v il or v ih , but no other value.
26 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 product ordering information environmental attribute e 1 = non-pb package modifier k = 48 leads or balls q = 48 balls or bumps (66 possible positions) package type b3 = tfbga (0.8mm pitch, 6mm x 8mm) c1 = xflga (0.5mm pitch, 4mm x 6mm) e = tsop (type 1, die up, 12mm x 20mm) m1 = wfbga (0.5mm pitch, 4mm x 6mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 45 = 45 ns 55 = 55 ns 70 = 70 ns version a = special feature version device density 800 = 8 mbit 400 = 4 mbit 200 = 2 mbit voltag e l = 3.0-3.6v v = 2.7-3.6v product series 39 = multi-purpose flash 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. sst 39 vf 200a - 70 - 4c - b3k e xx x x xxxx - xxx -xx -xxx x
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 27 ?2007 silicon storage technology, inc. s71117-09-000 2/07 valid combinations for sst39lf200a SST39LF200A-45-4C-EK sst39lf200a-45-4c-b3k SST39LF200A-45-4C-EKe sst39lf200a-45-4c-b3ke sst39lf200a-55-4c-ek sst39lf200a-55-4c-b3k sst39lf200a-55-4c-eke sst39lf200a-55-4c-b3ke valid combinations for sst39vf200a sst39vf200a-70-4c-ek sst39vf200a-70-4c-b3k sst39vf200a-70-4c-m1q sst39vf200a-70-4c-eke sst39vf200a-70-4c-b3ke sst39vf200a-70-4c-m1qe sst39vf200a-70-4i-ek sst39vf200a-70-4i-b3k sst39vf200a-70-4i-m1q sst39vf200a-70-4i-eke sst39vf200a-70-4i-b3ke sst39vf200a-70-4i-m1qe valid combinations for sst39lf400a sst39lf400a-55-4c-ek sst39lf400a-55-4c-b3k sst39lf400a-55-4c-eke sst39lf400a-55-4c-b3ke valid combinations for sst39vf400a sst39vf400a-70-4c-ek sst39vf400a-70-4c-b3k sst39vf400a-70-4c-c1q sst39vf400a-70-4c-m1q sst39vf400a-70-4c-eke sst39vf400a-70-4c-b3ke sst 39vf400a-70-4c-c1qe sst39vf400a-70-4c-m1qe sst39vf400a-70-4i-ek sst39vf400a-70-4i-b3k sst39vf400a-70-4i-c1q sst39vf400a-70-4i-m1q sst39vf400a-70-4i-eke sst39vf400a-70-4i-b3ke sst39vf400a-70-4i-c1qe sst39vf400a-70-4i-m1qe valid combinations for sst39lf800a sst39lf800a-55-4c-ek sst39lf800a-55-4c-b3k sst39lf800a-55-4c-eke sst39lf800a-55-4c-b3ke valid combinations for sst39vf800a sst39vf800a-70-4c-ek sst39vf800a-70-4c-b3k sst39vf800a-70-4c-c1q sst39vf800a-70-4c-m1q sst39vf800a-70-4c-eke sst39vf800a-70-4c-b3ke sst 39vf800a-70-4c-c1qe sst39vf800a-70-4c-m1qe sst39vf800a-70-4i-ek sst39vf800a-70-4i-b3k sst39vf800a-70-4i-c1q sst39vf800a-70-4i-m1q sst39vf800a-70-4i-eke sst39vf800a-70-4i-b3ke sst39vf800a-70-4i-c1qe sst39vf800a-70-4i-m1qe note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations.
28 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 packaging diagrams figure 22: 48-lead thin small outline package (tsop) 12mm x 20mm sst package code: ek 1.05 0.95 0.70 0.50 18.50 18.30 20.20 19.80 0.70 0.50 12.20 11.80 0.27 0.17 0.15 0.05 48-tsop-ek-8 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm 0- 5 detail pin # 1 identifier 0. 50 bsc
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 29 ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 23: 48-ball thin-profile, fine-pitch ball grid array (tfbga) 6mm x 8mm sst package code: b3k figure 24: 48-ball very-very-thin-profile, fine-pitch ball grid array (wfbga) 4mm x 6mm sst package code: m1q a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm l k j h g f e d c b a abcdefghjkl 6 5 4 3 2 1 6 5 4 3 2 1 0.50 0.50 bottom view 4.00 0.08 0.32 0.05 (48x) a1 indicator 4 6.00 0.08 2.50 5.00 a1 corner top view 48-wfbga-m1q-4x6-32mic-5 note: 1. although many dimensions are similar to those of jedec publication 95, mo-225, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. no ball is present in position a1; a gold-colored indicator is present. 5. ball opening size is 0.29 mm ( 0.05 mm) 1mm detail side view seating plane 0.20 0.06 0.63 0.10 0.08
30 data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39 lf400a / sst39lf800a sst39vf200a / sst39vf4 00a / sst39vf800a ?2007 silicon storage technology, inc. s71117-09-000 2/07 figure 25: 48-bump extremely-thin-profile, fine -pitch land grid array (xflga) 4mm x 6mm sst package code: c1q l k j h g f e d c b a abcdefghjkl 6 5 4 3 2 1 6 5 4 3 2 1 0.50 0.50 bottom view 4.00 0.08 0.29 0.05 (48x) a1 indicator 4 6.00 0.08 2.50 5.00 a1 corner top view 48-xflga-c1q-4x6-29mic-5 note: 1. although many dimensions are similar to those of jedec publication 95, mo-222, this specific package is not registere d. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. no bump is present in position a1; a gold-colored indicator is present. 1mm detail side view seating plane 0.04 + 0.025/ - 0.015 0.52 max. 0.473 nom. 0.08
data sheet 2 mbit / 4 mbit / 8 mbit multi-purpose flash sst39lf200a / sst39lf400a / sst39lf800a sst39vf200a / sst39vf400a / sst39vf800a 31 ?2007 silicon storage technology, inc. s71117-09-000 2/07 table 17: revision history number description date 04 ? 2002 data book may 2002 05 ? added footnotes for mpf power usage and typical conditions to table 10 on page 12 ? clarified the test conditions for power supply current and read parameters in table 10 on page 12 ? part number changes - see page 27 for additional information ? new micro-package part numbers added for sst39vf400a and sst39vf800a mar 2003 06 ? new micro-package part numbers added for sst39vf400a / 800a (see page 27) oct 2003 07 ? 2004 data book ? updated the b3k, m1q, and c1q package diagrams ? added non-pb mpns and removed footnote (see page 27) nov 2003 08 ? added m1q/m1qe mpns for the sstvf200a device on page 27 ? removed 90ns mpns and footnote for the sstvfx00a devices on page 27 ? added rohs compliance information on page 1 and in the ?product ordering informa- tion? on page 26 ? clarified the solder temperature profile under ?absolute maximum stress ratings? on page 11. apr 2005 09 ? removed valid combinations sst39lf400a-45-4c-ek, sst39lf400a-45-4c-b3k, sst39lf400a-45-4c-eke, and sst39lf400a-45-4c-b3ke due to eol ? applied new format styles. feb 2007 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

▲Up To Search▲

Price & Availability of SST39LF200A-45-4C-EK

	To Download SST39LF200A-45-4C-EK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .